CMOS imagers are increasingly being used as low cost imaging devices. A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. A readout circuit is connected to each pixel cell and includes at least pixel selecting field effect transistor formed in the substrate and a charge storage region formed on the substrate connected to the gate of a transistor coupled to the pixel selecting transistor. The charge storage region may be constructed as a floating diffusion region. The imager may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state before the transfer of charge to it; (4) transfer of charge to the storage region accompanied by charge amplification; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing a reset voltage and a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the storage region. The charge at the storage region is typically converted to a pixel output voltage by a source follower output transistor.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630 to Rhodes, U.S. Pat. No. 6,376,868 to Rhodes, U.S. Pat. No. 6,310,366 to Rhodes et al., U.S. Pat. No. 6,326,652 to Rhodes, U.S. Pat. No. 6,204,524 to Rhodes, and U.S. Pat. No. 6,333,205 to Rhodes, all assigned to Micron Technology, Inc. The disclosures of each of the foregoing are hereby incorporated by reference herein in their entirety.
To provide context for the invention, an exemplary CMOS APS (active pixel sensor) cell 10 is described below with reference to FIGS. 1 and 2. FIG. 1 is a top-down view of pixel cell 10; and FIG. 2 is a cross-sectional view of the cell 10, take along line A-A′ of FIG. 1. The cell 10 is a four transistor (4T) pixel sensor cell. The illustrated cell 10 shown includes a photodiode 13 formed as a pinned photodiode as shown in FIG. 2. Alternatively, the CMOS APS cell 10 may include a photogate, photoconductor or other photon to charge converting device, in lieu of a pinned photodiode 13, as the initial accumulating area for photo-generated charge. The photodiode 13 includes a p+ surface accumulation layer 5 and an underlying n− accumulation region 14 in a p-type semiconductor substrate layer 1.
The cell 10 of FIG. 1 has a transfer gate 7 for transferring photocharges generated in the n− accumulation region 14 to a floating diffusion region 3 (storage node). The floating diffusion region 3 is further connected to a gate 27 of a source follower transistor. The source follower transistor provides an output signal to a row select access transistor having gate 37 for selectively gating the output signal to a pixel array column line, shown as the out line in FIG. 1. A reset transistor having gate 17 resets the floating diffusion region 3 to a specified charge level before each charge transfer from the n− region 14 of the photodiode 13.
Referring to FIG. 2, the pinned photodiode 13 is formed on a p-type substrate base 1; alternatively, the photodiode 13 can be formed in a p-type epitaxial layer (not shown) grown on a substrate base. It is also possible, for example, to have a p-type substrate base beneath p-wells in an n-type epitaxial layer. The n− accumulation region 14 and p+ accumulation region 5 of the photodiode 13 are spaced between an isolation region 9 and a charge transfer transistor gate 7. The illustrated, pinned photodiode 13 has a p+/n−/p− structure.
The photodiode 13 has two p-type regions 5, 1 having a same potential so that the n− accumulation region 14 is fully depleted at a pinning voltage (Vpin). The photodiode 13 is termed “pinned” because the potential in the photodiode is pinned to a constant value, Vpin) when the photodiode 13 is fully depleted. When the transfer gate 7 is conductive, photo-generated charge is transferred from the charge accumulating n− region 14 to the floating diffusion region 3. A complete transfer of charge takes place when a voltage on the floating diffusion region 3 remains above Vpin while the pinned photodiode functions at a voltage below Vpin. An incomplete transfer of charge results in image lag.
The isolation region 9 is typically formed using a conventional shallow trench isolation (STI) process or by using a Local Oxidation of Silicon (LOCOS) process. The floating diffusion region 3 adjacent to the transfer gate 7 is commonly n− type. Translucent or transparent insulating layers, color filters, and lens structures are also formed over the cell 10.
Additionally, impurity doped source/drain regions 32 (FIG. 1), having n-type conductivity, are provided on either side of the transistor gates 17, 27, 37. Conventional processing methods are used to form contacts (not shown) in an insulating layer to provide an electrical connection to the source/drain regions 32, the floating diffusion region 3, and other wiring to connect to gates and form other connections in the cell 10.
Generally, in CMOS pixel cells, such as the cell 10 of FIGS. 1 and 2, incident light causes electrons to collect in the accumulation n− region 14. An output signal produced by the source follower transistor having gate 27 is proportional to the number of electrons extracted from the n− accumulation region 14. The maximum output signal increases with increased electron capacitance or acceptability of the n− region 14 to acquire electrons. In this example, the p+/n− junction dominates the capacitance of the pinned photodiode 13.
In a pixel imager cell having a pinned photodiode as just described, blue light, and other short wavelength light, are typically absorbed at the top of the junction of the p+/n− regions while red light is absorbed at the bottom of the n-type accumulation region. For example, at room temperature, red light (λ=approximately 700 nm) will penetrate approximately 3.0 microns deep into polysilicon, while violet light (λ=approximately 400 nm) will only penetrate approximately 0.2 microns deep. It becomes very critical, therefore, to create a very shallow p/n junction near the top of the pixel cell surface in order to improve the quantum efficiency of the cell when exposed to shorter wavelengths of light. Moreover, the surface p-type layer should be of significantly high concentration so that it does not get depleted at bias conditions when the bottom n-type layer gets fully depleted.
It is difficult using the conventional methods of implant engineering to create a pinned photodiode having these desired characteristics. Either the process requires significant and challenging mask levels and implant conditions (which can be costly) or potential barriers and wells may develop in the photo-sensing area, decreasing the quantum efficiency of the cell. Furthermore, as the size of pixel cells continues to decrease due to desired scaling, implant optimization becomes increasingly more difficult.
There is needed, therefore, a pixel cell having a pinned photodiode with a shallow junction having minimal potential barriers. Also needed is a simple method of fabricating a pixel cell having these desired characteristics.